This invention relates to data processing apparatus and, more specifically, is concerned with a multi-processor data processing system.
A data processing system generally has a number of interrupt lines, for carrying interrupt signals from various sources, such as peripheral devices. In a multi-processor system the question arises of how these interrupts are to be allocated to the processors,
U.S. Pat. No. 3,421,150 described a multi-processor data processing system having an interrupt directory circuit which assigns the highest priority pending interrupt request to the processor currently having the lowest interruptability index code; that is, to the most available processor.
"VLSI assist for a multi-processor", B. Beck et al, Operating Systems Review, Vol 21, No. 4, October 1987 pages 10-20, describes a multi-processor system having a system link and interrupt controller (SLIC) subsystem, which dynamically allocates interrupt requests to those processors running the least important processes.
A problem with these prior art systems is that they require special hardware for deciding which of the processors is to handle each interrupt. The object of the present invention is to avoid this problem, while still achieving balancing of the interrupt load among the processors.